Analytical Modeling and Reduction of Direct Tunneling Current during Behavioral Synthesis of Nanometer CMOS Circuits

Gate oxide direct tunneling current is the major component of static power dissipation of a CMOS circuit for low-end technology, where the gate dielectric (SiO2) thickness is very low. This paper presents a novel direct tunneling current reduction method during behavioral synthesis of nanometer CMOS circuits. We provide analytical models to calculate the direct tunneling current and the propagation delay of behavioral level components. We then characterize those components for various gate oxide thicknesses. We also provide an algorithm for behavioral scheduling for minimizing the overall tunneling current dissipation of datapath circuits. The algorithm explores dual oxide thickness option for reducing direct tunneling current. We have carried out extensive experiments for various behavioral level benchmarks under various resource constraints and observed significant reductions in tunneling current.